Xbox One:Xbox One X M.2 SSD Mod
Xbox One S M.2 SSD Modification Tutorial
This method and the instructions were created by @craftbenmine.
Original in-depth video
Overall Parts List
Note: All resistors are 0402 package unless otherwise specified
| Component | Value | Package | Quantity | Notes |
|---|---|---|---|---|
| R99, R95, R92, R96, R101, R104, R117, R118, R103, R100, R635 | 0Ω | 0402 | 11 | Clock line and power enable jumpers |
| R328 | 511Ω | 0402 | 1 | Debug LED resistor (500-700Ω acceptable) |
| R637, R462, R432, R85, R87, R91 | 10kΩ | 0402 | 6 | Various pull-up/discharge resistors |
| FB1 | 1000Ω 200mA | 0402 | 1 | Ferrite bead |
| D8 | 3V LED | - | 1 | Optional debug indicator |
| Q3 | NTTFS4C50N | - | 1 | Load switch |
| U35 | 9DBV0541 | - | 1 | Clock buffer IC |
| J32 | MDT420M01002 | - | 1 | M.2 connector (Amphenol CS/FCI) |
| C1085, C1087, C1082, C1083, C1080, C1081, C1067, C1068, C550, C564, C568, C181, C125 | 0.1µF 16V | 0402 | 13 | Decoupling/protection capacitors |
| C448, C449, C434, C1075, C1078 | 1µF 6.3V | 0402 | 5 | Decoupling capacitors |
| C450 | 4.7µF 6.3V | 0603 | 1 | Decoupling capacitor |
| C581 | 10µF 6.3V | 0603 | 1 | Bulk capacitor |
| C446 | 22µF 6.3V | 0805 | 1 | Bulk capacitor |
This tutorial covers the steps needed to add M.2 SSD support to an Xbox One X. The modification consists of four main areas that need to be addressed.
1. Power and Reset Signal (V_3p3_M2 and PCIe_RESET)
1.1 PCIe Reset Signal Modification
The M.2 SSD has an internal pull-up resistor on its PCIe_RESET input. We need to isolate the PCIE_RST_N signal from the southbridge output by using a double inverter configuration.
Required components:
| Component | Value | Package | Quantity |
|---|---|---|---|
| U63, U66 | SSM3K324R | - | 2 |
| R283, R293 | 10kΩ | 0402 | 2 |
| R318, R307 | 100Ω | 0402 | 2 |
| C433 | 0.022µF 50V | 0402 | 1 |
1.2 V_3p3_M2 Power Supply
The M.2 SSD requires 3.3V power (V_3p3_M2) supplied through a load switch (Q3). The power enable signal (M2_ENABLE_C) is controlled via an op-amp (U34).
Required components:
| Component | Value | Package | Quantity | Notes |
|---|---|---|---|---|
| R635 | 0Ω | 0402 | 1 | Required for M2_PWR_EN signal |
| R637 | 10kΩ | 0402 | 1 | Discharge resistor |
| Q3 | NTTFS4C50N | - | 1 | Load switch |
| C450 | 4.7µF 6.3V | 0603 | 1 | Decoupling |
| C448, C449, C434 | 1µF 6.3V | 0402 | 3 | Decoupling |
| C446 | 22µF 6.3V | 0805 | 1 | Bulk capacitance |
| R328* | 511Ω | 0402 | 1 | Optional debug LED resistor |
| D8* | 3V LED | - | 1 | Optional activity indicator |
*Optional debug components
2. M.2 Slot Installation
The M.2 slot requires decoupling capacitors for the data lines and 3.3V power.
Required components:
| Component | Value | Package | Quantity | Notes |
|---|---|---|---|---|
| J32 | MDT420M01002 | - | 1 | M.2 connector |
| C1085-C1068 | 0.1µF 16V | 0402 | 8 | Data line protection |
| C1075, C1078 | 1µF 6.3V | 0402 | 2 | V_3p3_M2 decoupling |
3. Clock Strapping Modifications
The clock configuration needs to be modified when installing the M.2 SSD since we're implementing a clock buffer. This requires removing existing resistors and adding new ones.
Components to remove:
- R464, R456, R435, R427, R419, R411
- R423, R428, R443, R449, R459, R460
New components to add:
| Component | Value | Package | Quantity | Notes |
|---|---|---|---|---|
| R462, R432 | 10kΩ | 0402 | 2 | APU clock noise prevention |
| C550, C564, C568 | 0.1µF 16V | 0402 | 3 | Clock buffer decoupling |
| C581 | 10µF 6.3V | 0603 | 1 | Bulk capacitance |
4. Clock Buffer Installation
The clock buffer replaces the southbridge clocks with four new clock signals. It uses the ethernet clock as a reference to generate clocks for the ethernet IC, M.2 slot, and APU.
Required components:
| Component | Value | Package | Quantity | Notes |
|---|---|---|---|---|
| U35 | 9DBV0541 | - | 1 | Clock buffer IC |
| FB1 | 1000Ω 200mA | 0402 | 1 | Ferrite bead |
| C181, C125 | 0.1µF 16V | 0402 | 2 | Decoupling |
| R99-R100 | 0Ω | 0402 | 10 | Clock line jumpers |
| R85, R87, R91 | 10kΩ | 0402 | 3 | Pull-up resistors |
Clock Buffer Configuration Notes:
- Clock buffer runs on 1.8V (V_CLKBUFF) derived from V_SOC1P8
- Clock 0 is deactivated by pulling OE0_N high
- SMBus clock and data are tied high to V_SOC1P8
- All clock inputs and outputs are jumpered with 0Ω resistors
Original modification tutorial @ Discord: Discord craftbenmine