Xbox 360:RGH/RGH1.2: Difference between revisions

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==Glitch Chip Installation==
==Glitch Chip Installation==
[[File:Phat360PLLFix.jpg|thumb|400x400px|PLL Repair on a Phat motherboard (required if bottom pad is damaged). Image credit to TheLazyITGuy.]][[File:1v8-X360ACE.jpg|thumb|1.8v on an Ace V3]]


===Motherboard points===
===Motherboard points===
[[File:Phat360PLLFix.jpg|thumb|400x400px|PLL Repair on a Phat motherboard (required if bottom pad is damaged). Image credit to TheLazyITGuy.]]
====[[Xbox 360:RGH/Solder Points#Phat|Phat (Non-Xenon)]]====


====Phat (Non-Xenon)====
====[[Xbox 360:RGH/Solder Points#Slim (Trinity)|Slim (Trinity)]]====
 
==== [[Xbox 360:RGH/Solder Points#Slim or E (Corona/Waitsburg/Stingray)|Slim or E (Corona/Waitsburg/Stingray)]]====
* 3.3v <br>[[File:Y5p0dxP.jpg|331x331px]]
*1.8V '''(Only if using an X360 ACE)''' <br>[[File:1v8-HDMI.png|frameless]]
*PLL
** Bottom <br>[[File:Fat360PLL.jpg|frameless|290x290px]]
**Top (under CPU heatsink; requires scraping) <br>[[File:Fat360topPLL.jpg|frameless|288x288px]]
*STBY_CLK
**Bottom <br>[[File:CLK.png|frameless|287x287px]]
**Top (There are 2 points boxed; either can be used.) <br>[[File:Fat360STBY CLK.jpg|frameless|286x286px]]
*POST
**Bottom <br>[[File:Post.png|frameless|287x287px]]
**Top (requires scraping) <br>[[File:FT6U1 topside.png|frameless|285x285px]]
*CPU_RST
**R8C2 (Performs better) <br>[[File:VXi9LgC.jpg|frameless|311x311px]]
**C7R112 <br>[[File:RST.png|frameless]]
**J8C1: <br>[[File:Cp2OBF3.jpeg|frameless|338x338px]]
*GND
**Near 3.3v <br>[[File:J2b1gnd.png|frameless|282x282px]]
**AV Port
**Any other ground point
 
====Slim (Trinity)====  
*PLL <br>[[File:RGH1.2 Slim PLL.jpg|frameless|330x330px]]
**No alternative point!
* CPU_CLK <br>'''(Only if using an X360 ACE V4/V5)'''
**Top <br>[[File:TrinityC1C2.png|frameless]]
***There are two points circled for C1 and C2 respectively; either can be used or bridged.
**Bottom <br>[[File:TrinityBottomC1C2.png|frameless]]
*POST & RST <br>[[File:TrinityPOSTandRST.png|frameless|328x328px]]
**There are two RST points, either can be used.
**A Postfix adapter can be used on Trinity in case it's damaged.
*STBY_CLK
**C3B10 (Top) <br>[[File:TrinityHanaCLK.jpg|frameless]]
**FT3N2 (Bottom) <br>[[File:Ft3n2.jpg|frameless|301x301px]]
*GND & 3.3V <br>[[File:Trinity 3v3GND.png|frameless|350x350px]]
 
==== Slim/E (Corona)====
[[File:5lY3TID.png|thumb]]
*PLL<br>[[File:RGH1.2 Slim PLL.jpg|frameless|329x329px]]
**No alternative point!
*CPU_CLK '''(Only if using an X360 ACE V4/V5)'''<br>[[File:CoronaCPUCLK.png|frameless|328x328px]]
**There are two points circled for C1 and C2 respectively, either can be used or bridged.
* POST & RST<br>[[File:Corona POSTandRST.png|frameless|327x327px]]
**There are two RST points, either can be used.
**If POST on the bottom is disabled (like in Waitsburg & Stingray boards) or damaged, a postfix adapter is required.
*GND & 3.3V <br>[[File:Corona 3v3GND.png|frameless|325x325px]]
=== Glitch chip pinouts & diagrams===
=== Glitch chip pinouts & diagrams===


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*Pinout follows written labels
*Pinout follows written labels
*Don't use POST or RST tuners
*Don't use POST or RST tuners
[[File:1v8-X360ACE.jpg|thumb|1.8v on an Ace V3]]
=====[[:File:X360acergh12phatinstalldiagram.png|X360ACE (V1/V2/V3), DGX]]=====  
=====[[:File:X360acergh12phatinstalldiagram.png|X360ACE (V1/V2/V3), DGX]]=====  
*C - POST
*C - POST

Revision as of 00:34, 5 September 2023

RGH1.2 combines RGH1-like PLL slowdown with Glitch2 images to allow reliable glitching of Falcon/Jasper consoles with split CB (post 14699 kernel). RGH1.2 V2 ports this hack to Trinity/Corona consoles as well as fixing a few issues on Jaspers.

Equipment Needed

Glitch Chip Installation

PLL Repair on a Phat motherboard (required if bottom pad is damaged). Image credit to TheLazyITGuy.
1.8v on an Ace V3

Motherboard points

Phat (Non-Xenon)

Slim (Trinity)

Slim or E (Corona/Waitsburg/Stingray)

Glitch chip pinouts & diagrams

Phat

Coolrunner Rev A/B/C/D
  • A - PLL
  • B - STBY_CLK (only if not using oscillator)
  • C - POST
  • D - RST
CR3 Lite
  • A - PLL
  • B - STBY_CLK (only if not using oscillator)
  • C - POST
  • D - RST
Matrix Glitcher
  • A - RST
  • B - POST
  • C - STBY_CLK (only if not using oscillator)
  • F - PLL
Squirt
  • Squirt BGA 1.2: Disable the onboard 670pf and/or 480pf caps by removing R7 and R8
  • Squirt Reloaded 2.X: remove R2 and connect STBY_CLK
  • Pinout follows written labels
  • Don't use POST or RST tuners
X360ACE (V1/V2/V3), DGX
  • C - POST
  • D - RST
  • E - STBY_CLK (only if not using oscillator version)
  • F - PLL (22K ohm resistor required)
  • Remember to remove the diode and connect 1.8V

Slim

Coolrunner Rev A/B/C/D
  • B - STBY_CLK (only if not using oscillator)
  • C - POST
  • D - RST
  • E - PLL (10K ohm resistor recommended)
CR3 Lite
  • B - STBY_CLK (only if not using oscillator)
  • C - POST
  • D - RST
  • E - PLL (10K ohm resistor recommended)
Matrix Glitcher (Corona)
  • A - RST
  • B - POST
  • E - PLL (10K ohm resistor recommended)
Matrix Glitcher (Trinity)
  • A - RST
  • B - POST
  • C - STBY_CLK (only if not using oscillator)
  • E - PLL (10K ohm resistor recommended)
X360ACE (V1/V2/V3/V3+), DGX
  • C - POST
  • D - RST
  • F - PLL (10K ohm resistor recommended)
X360ACE V4/V5
  • A - RST
  • B - POST
  • C1 - CPU_CLK_DP
  • C2 - CPU_CLK_DN
  • D - PLL (10K ohm resistor required)
Squirt
  • Squirt Reloaded 2.X: remove R2 and connect STBY_CLK or remove 100 MHz and add 48 MHz oscillator
  • Use SCL pad for PLL
  • Pinout follows written labels
  • Don't use POST or RST tuners

Programming the Glitch Chip

  1. Plug the cable from your programmer into the chip programmer.
    • If you are using an xFlasher, ensure the switch is set to SPI.
    • CoolRunner: Slide switch to "PRG".
  2. Open J-Runner with Extras. Click "Program Timing File" in the upper left and select your console’s tab and the relevant radio button for RGH 1.2.
  3. Click "Program". When complete, unplug the cable from the glitch chip.
    • Coolrunner: Set the switch back to "NOR".

X360ACE V4/V5/V3+

Decrypting the NAND

  1. Connect Ethernet and power on the console. The glitch chip should blink once or more times, and then the console should start into XeLL RELOADED.
  2. Once XeLL finishes, it will display your CPU key and some other info. There is also an IP address.
  3. Enter the IP address into the box on the lower right of J-Runner and click "Get CPU Key". J-Runner will pull the info from the box, and decrypt the NANDs automatically.

Writing New NAND Image

  1. Power down the console, and connect your programmer to the motherboard.
    • If you are using an xFlasher, ensure the switch is set to SPI.
  2. In the upper right of J-Runner, ensure the Glitch2 radio button is selected.
    • Enable SMC+ for better boot times.
  3. Click "Create XeBuild Image". This will take a few moments.
  4. Click "Write NAND".
  5. Disconnect your programmer when the process completes.
  6. Boot the console several times and ensure it boots consistently. If not, make sure your wiring is clean and neat and avoids noisy area. Run the wires near the X-Clamps for best results.
  7. Return to the RGH main page and continue in the Cleaning Up section.
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